1. Field of the Invention
The present invention is directed to integrated circuit design software used in the manufacture of integrated circuits. More specifically, but without limitation thereto, the present invention is directed to a library of elements for synthesizing hardware description language (HDL) from register transfer level (RTL) code.
2. Description of the Prior Art
Identifying and estimating routing congestion in an integrated circuit design is one of the fundamental issues in very large scale integrated circuit (VLSI) design. In conventional software tools for synthesizing hardware description language (HDL) from register transfer level (RTL) code, components are selected from a library and mapped to a hardware description language. The routing congestion is then estimated using probabilistic models during trial circuit layout and floorplanning.